Capability memory reference instructions

Capability memory reference instructions will either load capability registers from memory, or store their contents into memory. The actual memory address will be computed in two steps, first an index is computed by the program and left in a data register, then the actual address is computed from this index and the contents of a capability register specified in the instruction. This specified capability-register must contain a capability of type capability-segment, and its base will be added to the given index. (If capabilities occupy more than one word of memory, the index will be suitably modified to guarantee that the resulting address will be that of the first word of a capability.) The index will also be checked against the bound. If a load is to be done, the capability-segment capability must have the load access bit on. Similarly, if a store is to be done, the store access bit must be on. In order to avoid having absolute addresses within the capabilities (as stored in memory), and to remain close to the CAL TSS ECS system, the same trick as used in the System 250 can be used. Instead of a base bound pair, a segment type capability, stored in memory, will contain a unique name and an index into an MOT. The indexed MOT entry will contain the same unique name (for checking purposes) and the actual base bound pair. When a segment type capability is loaded into a register, the MOT index will be followed, the unique name checked, and the actual base bound pair loaded. In this case, such a register will have to contain the original unique name and MOT index for subsequent storage. (Of course, this MOT index and unique name need not be kept in hardware registers, but in a known part of memory, as in the System 250.) On a machine like the CDC 6400, with an extra memory, any base bound pair could state which memory contained the address, thus reference to either memory would be the same. This would be true for both data segments as well as capability segments.