Hardware capabilities

The following hardware proposal combines the protected-base-bound-pairs of a system like MAGNUM or System 250 with the abstract typed objects of CAL TSS. In particular, it permits a program with proper authority to directly convert a capability for an abstract object into a capability for a base-bound-pair describing the storage area for the representation of the object. It combines the basic capability hardware of MAGNUM [F1], the MOT of CAL TSS (similar to an idea in System 250 [C4, E1]), the user type facility of CAL TSS, and a proposal of David Redell and Bruce Lindsay (the lock facility, intended by them for software implementation of such features of CAL TSS as the subprocess-descriptor). The Central Processor will have an architecture closer to that of MAGNUM or System 250 than that of the CDC 6400. There will be two classes of registers, capability and data. There will be four classes of instructions:

• capability memory ref
• data memory ref
• data manipulation
• capability manipulation

A capability-register will contain three fields:

• type
• access bits (These correspond to option bits in CAL TSS capabilities.)
• datum

There will be a number of types, six of which will be:

• capability segment (C-list)
• data segment
• datum
• create new lock and key authority
• lock
• key

For capability segment and data segment capabilities, the datum field will contain two subfields:

• base
• bound

For lock and key capabilities, the datum field will contain three subfields:

• source type
• target type
• access field check bits